Electronics Adventures

While I own a Raspberry Pi already, I was looking for a bare minimum ARM development board capable of running Linux and offers a good amount of I/O peripherals which the R-Pi lacks. I finally stumbled upon Arietta G25, a really tiny ARM board from acmesystems. This teeny tiny board costed just $35 from microcontrollershop.com . Arietta G25 Arietta G25 Features: ARM9 @ 400Mhz 128MB or 256MB DDR2 RAM UART, ADC, I2C, USB and lot more peripherals! My Setup: My laptop which will be the host here runs Arch Linux. The first step would be loading the image for Arietta in the microSD card. I downloaded Debian Wheezy Grip 7.7 image from  here  and wrote the image to a 4GB microSD card. The next step would be to setup an SSH connection between the Laptop and Arietta G25. Before that, let us disable the dhcp service in Arch Linux(Host). sudo systemctl stop dhcpcd.service If the image is correctly loaded into the microSD card, the red LED on Ariett...

  Here is the second part of the RISC Processor Design. I have implemented this Processor as a part of my ASIC Design Lab project  "Programmable Controller/Router and Peripheral Design with peripheral I/O multiplexing".  This project focuses of peripheral multiplexing to the GPIO pins of the processor in runtime. An example case will be a Pulse Width Modulated wave switching between any I/O pins during processor execution or an UART Transmitter pin routed to a pin based on board design without the need of external multiplexers.   The processor can access the peripherals via register write instructions. Similar to register file, the peripherals support two data reads and one data write simultaneously. Since I have used custom instructions, a custom Instruction Set Architecture (ISA) is also designed. BLOCK DIAGRAM: 16-bit Instruction Format : 1. Register Instruction: OPCODE [15:12] DEST[11:8] SRC_1 [7:4] SRC_2 [3:0] ...

  Low cost FPGA development platforms and Hardware Description Languages like Verilog & VHDL have not only made lives of Front-end VLSI  Engineers easier but also hobbyists' . I have been experimenting with a 40$ Xilinx FPGA development board for couple of years and its real fun. And now, a part of my project for ASIC Design Lab course at University of Minnesota requires me to design and implement a microprocessor. Armed with my FPGA board and a new-found enthusiasm amidst my busy schedule at the U of M, I sat up to design a minimalistic CPU in Verilog. Tools Used: Verilog/VHDL Simulator (ModelSim, Icarus Verilog, Xilinx ISE,etc) A decent Code Editor (VIM) A Xilinx FPGA board (optional) ARCHITECTURE:   I chose Load/Store Architecture for my microprocessor design since most RISC machines like ARM, MIPS,etc are based on this architecture. Besides that, quicker prototyping and better understanding of computer architecture was on top priority in my list...

JTAG - Joint Test Action Group is an IEEE 1149.1 standard used in many silicon devices for programming and debugging purposes. Xilinx FPGAs support this JTAG protocol for their configuration. Here I have designed a JTAG FPGA bitstream programmer using Raspberry Pi which programs the bit file into FPGA in fraction of seconds!  JTAG physical bus has four lines: TMS (Test Mode Select) TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) Components Used:  Raspberry-Pi Xilinx Spartan 3E FPGA (XC3S250E in Papilio One) Jumper wires BLOCK DIAGRAM: TAP CONTROLLER: The TAP(Test Access Port) controller is a state machine inside the FPGA which changes it's state based on TMS input. For instance, let us assume that the state machine is in " Test-Logic-Reset " state. Now if I drive the TMS pin low and toggle the TCK pin, the state machine will go to " Run-Test/ Idle " state. This is how we move to different states.  Note ...

Having worked with a variety of microcontrollers from AVR to ARM Cortex controllers, I bought a Xilinx FPGA dev board(papilio One) which around $40 to experiment. After getting comfortable with Verilog HDL, I implemented few data encoders-decoders, communication blocks and played around a while. Then my attention turned towards implementing a Soft-core Processor in FPGA. But I need my own instruction set and a Compiler for my soft-processor too. Besides, intensive googling taught me that there are tons of Soft-processor cores. Finally,I settled with ZPU which a 32-bit softcore processor for xilinx FPGA with good amount of peripherals ranging from timers to communication blocks like UART, SPI etc. It has support for VGA screen drivers too. PROJECT: This project was aimed to implement a system to play a small snippet of audio from FPGA's memory using ZPU - soft-core processor. Components used: Papilio One board- Xilinx Spartan XC3S250E A speaker Misc- Resistor...

 This week was quite hectic for me with course assignments and their merciless deadlines. One such assignment in Advanced Computer Architecture  was simulation of various benchmarks in alpha architecture in simplescalar , a well-known computer architecture simulator. I was supposed to run a total of 4 benchmarks with different configurations of cache memory, instruction issue widths, commit widths, in-order execution modes, etc and I had to plot the required performance parameters for every benchmark. A conservative estimate would be around 40 plots!  Since the simulation platform was Linux, I could breathe a sigh of relief since most things can be automated using a powerful tool called shell. Scripting made my life easier here since I can automate a bunch of simulations without having to keep an eye on each and every simulation which would take anywhere from 20 minutes to 20 hours.  The problem arose when it came to plotting the performance results. Becau...

Last month could have been never better without the "Electronics For you " design contest ' s results announcement. I was delighted to find my name at the 2nd place in the winner's list under Raspberry Pi category for my project named "Smiley-Pi". Very surprised that my previously discussed project in my blog turned out to be a prize winning project. So what is it?   Smiley - Pi   is a tiny Nokia caller LCD(extensively discussed here & here ) based status notifier for Raspberry-Pi. The name is derived from a mode of operation where it uses various smiley images to indicate system information like temperature. The tiny 0.9", 96x65 monochrome caller LCD of Nokia 2760 is interfaced through bit-banged SPI to the Raspberry-Pi. The base driver application is coded in C and higher level in shell & Python scripts. The user application can use any language which can invoke the driver binaries in it.   Many times we would have ...