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Showing posts from March, 2015

RTL Design & Implementation of a RISC- Single Cycle Processor -Part I

  Low cost FPGA development platforms and Hardware Description Languages like Verilog & VHDL have not only made lives of Front-end VLSI  Engineers easier but also hobbyists' . I have been experimenting with a 40$ Xilinx FPGA development board for couple of years and its real fun. And now, a part of my project for ASIC Design Lab course at University of Minnesota requires me to design and implement a microprocessor. Armed with my FPGA board and a new-found enthusiasm amidst my busy schedule at the U of M, I sat up to design a minimalistic CPU in Verilog. Tools Used: Verilog/VHDL Simulator (ModelSim, Icarus Verilog, Xilinx ISE,etc) A decent Code Editor (VIM) A Xilinx FPGA board (optional) ARCHITECTURE:   I chose Load/Store Architecture for my microprocessor design since most RISC machines like ARM, MIPS,etc are based on this architecture. Besides that, quicker prototyping and better understanding of computer architecture was on top priority in my list in this p