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Showing posts from 2015

My badge Hack at Hackaday Superconference 2015

  November was a good time for many hackers and makers around and outside California who got to attend the Hackaday's Superconference 2015. Power-packed with technical workshops, project presentations and badge hacking , this Superconference was one of the best platforms for the best minds around the world. It was my first hardware conference in United States and I was super-excited to attend. The most awaited event - Badge hacking started with a blast. Right side of the presentation room were full of people who were soldering and modding their badges for the badge hacking contest. I too joined the group of geeks and started my work. What did I do?   There were tons of free development boards, components and tools available at the table for us to use in our badge. I took a teensy LC which had a 32-bit ARM Cortex M0+ freescale microcontroller powerful enough to design what I had in my mind. I had an idea of making a platform independent USB game controller which can work on an

Arietta G25 - an Atmel ARM9 board

While I own a Raspberry Pi already, I was looking for a bare minimum ARM development board capable of running Linux and offers a good amount of I/O peripherals which the R-Pi lacks. I finally stumbled upon Arietta G25, a really tiny ARM board from acmesystems. This teeny tiny board costed just $35 from . Arietta G25 Arietta G25 Features: ARM9 @ 400Mhz 128MB or 256MB DDR2 RAM UART, ADC, I2C, USB and lot more peripherals! My Setup: My laptop which will be the host here runs Arch Linux. The first step would be loading the image for Arietta in the microSD card. I downloaded Debian Wheezy Grip 7.7 image from  here  and wrote the image to a 4GB microSD card. The next step would be to setup an SSH connection between the Laptop and Arietta G25. Before that, let us disable the dhcp service in Arch Linux(Host). sudo systemctl stop dhcpcd.service If the image is correctly loaded into the microSD card, the red LED on Arietta board will start

RTL Design & Implementation of a RISC Processor and Peripheral Multiplexer -Part II

  Here is the second part of the RISC Processor Design. I have implemented this Processor as a part of my ASIC Design Lab project  "Programmable Controller/Router and Peripheral Design with peripheral I/O multiplexing".  This project focuses of peripheral multiplexing to the GPIO pins of the processor in runtime. An example case will be a Pulse Width Modulated wave switching between any I/O pins during processor execution or an UART Transmitter pin routed to a pin based on board design without the need of external multiplexers.   The processor can access the peripherals via register write instructions. Similar to register file, the peripherals support two data reads and one data write simultaneously. Since I have used custom instructions, a custom Instruction Set Architecture (ISA) is also designed. BLOCK DIAGRAM: 16-bit Instruction Format : 1. Register Instruction: OPCODE [15:12] DEST[11:8] SRC_1 [7:4] SRC_2 [3:0] 2.

RTL Design & Implementation of a RISC- Single Cycle Processor -Part I

  Low cost FPGA development platforms and Hardware Description Languages like Verilog & VHDL have not only made lives of Front-end VLSI  Engineers easier but also hobbyists' . I have been experimenting with a 40$ Xilinx FPGA development board for couple of years and its real fun. And now, a part of my project for ASIC Design Lab course at University of Minnesota requires me to design and implement a microprocessor. Armed with my FPGA board and a new-found enthusiasm amidst my busy schedule at the U of M, I sat up to design a minimalistic CPU in Verilog. Tools Used: Verilog/VHDL Simulator (ModelSim, Icarus Verilog, Xilinx ISE,etc) A decent Code Editor (VIM) A Xilinx FPGA board (optional) ARCHITECTURE:   I chose Load/Store Architecture for my microprocessor design since most RISC machines like ARM, MIPS,etc are based on this architecture. Besides that, quicker prototyping and better understanding of computer architecture was on top priority in my list in this p

JTAG - Test Access Port (TAP)Controller based Xilinx FPGA configuration using Raspberry Pi

JTAG - Joint Test Action Group is an IEEE 1149.1 standard used in many silicon devices for programming and debugging purposes. Xilinx FPGAs support this JTAG protocol for their configuration. Here I have designed a JTAG FPGA bitstream programmer using Raspberry Pi which programs the bit file into FPGA in fraction of seconds!  JTAG physical bus has four lines: TMS (Test Mode Select) TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) Components Used:  Raspberry-Pi Xilinx Spartan 3E FPGA (XC3S250E in Papilio One) Jumper wires BLOCK DIAGRAM: TAP CONTROLLER: The TAP(Test Access Port) controller is a state machine inside the FPGA which changes it's state based on TMS input. For instance, let us assume that the state machine is in " Test-Logic-Reset " state. Now if I drive the TMS pin low and toggle the TCK pin, the state machine will go to " Run-Test/ Idle " state. This is how we move to different states.  Note