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Showing posts from April, 2015

RTL Design & Implementation of a RISC Processor and Peripheral Multiplexer -Part II

  Here is the second part of the RISC Processor Design. I have implemented this Processor as a part of my ASIC Design Lab project  "Programmable Controller/Router and Peripheral Design with peripheral I/O multiplexing".  This project focuses of peripheral multiplexing to the GPIO pins of the processor in runtime. An example case will be a Pulse Width Modulated wave switching between any I/O pins during processor execution or an UART Transmitter pin routed to a pin based on board design without the need of external multiplexers.   The processor can access the peripherals via register write instructions. Similar to register file, the peripherals support two data reads and one data write simultaneously. Since I have used custom instructions, a custom Instruction Set Architecture (ISA) is also designed. BLOCK DIAGRAM: 16-bit Instruction Format : 1. Register Instruction: OPCODE [15:12] DEST[11:8] SRC_1 [7:4] SRC_2 [3:0] 2.