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Showing posts from January, 2015

JTAG - Test Access Port (TAP)Controller based Xilinx FPGA configuration using Raspberry Pi

JTAG - Joint Test Action Group is an IEEE 1149.1 standard used in many silicon devices for programming and debugging purposes. Xilinx FPGAs support this JTAG protocol for their configuration. Here I have designed a JTAG FPGA bitstream programmer using Raspberry Pi which programs the bit file into FPGA in fraction of seconds!  JTAG physical bus has four lines: TMS (Test Mode Select) TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) Components Used:  Raspberry-Pi Xilinx Spartan 3E FPGA (XC3S250E in Papilio One) Jumper wires BLOCK DIAGRAM: TAP CONTROLLER: The TAP(Test Access Port) controller is a state machine inside the FPGA which changes it's state based on TMS input. For instance, let us assume that the state machine is in " Test-Logic-Reset " state. Now if I drive the TMS pin low and toggle the TCK pin, the state machine will go to " Run-Test/ Idle " state. This is how we move to different states.  Note