Skip to main content

Audio Playback using ZPU-Soft Processor in FPGA

Having worked with a variety of microcontrollers from AVR to ARM Cortex controllers, I bought a Xilinx FPGA dev board(papilio One) which around $40 to experiment. After getting comfortable with Verilog HDL, I implemented few data encoders-decoders, communication blocks and played around a while.
Then my attention turned towards implementing a Soft-core Processor in FPGA. But I need my own instruction set and a Compiler for my soft-processor too. Besides, intensive googling taught me that there are tons of Soft-processor cores.
Finally,I settled with ZPU which a 32-bit softcore processor for xilinx FPGA with good amount of peripherals ranging from timers to communication blocks like UART, SPI etc. It has support for VGA screen drivers too.


This project was aimed to implement a system to play a small snippet of audio from FPGA's memory using ZPU - soft-core processor.

Components used:
  • Papilio One board- Xilinx Spartan XC3S250E
  • A speaker
  • Misc- Resistors and capacitors


The audio signal is recorded in nero wave editor and converted to 8-bit, 8000samples/second mono PCM wave format. This audio data from this file is extracted using FILE I/O functions in Cpp and stored as and array. This array of data is written to a file in the format of a variable array holding these values. This variable array is used in soft processor code.

The audio data looks as follows:

The PWM feature is used to generate analog audio output from the given data. I have used 80khz as carrier wave which is 10 times that of sampling rate(8000).

  PWM frequency= 10 x sampling rate = 10 x 8000 = 80KHz

This means that we have 10 PWM waves per sample to represent the analog voltage. The duty cycle of these waves are varied to generate the required voltage level. 

Duty cycle = % of time for which the wave is logic "HIGH"  ie. Ton /(Ton+Toff)

Since the audio data is 8 bit wide, the values range from 0-255 ( 0 - 2^8); which means 0 corresponds to 0% duty cycle and 255 corresponds to 100% duty cycle.For example, if sample 1 has the value 127, 10 waves with 50% duty cycle are generated immediately to generate the voltage (Around 1.65V = 50% of 3.3V)

So repeating the above process for all the 8000 samples per second, we can generate a decent analog wave form similar to the audio data.


Here I have recorded my name "Bharathi" and stored as array of data in the code and programmed the FPGA. The audio quality is bearable since I have used a tiny piezo speaker and I have not used proper filtering of noise using RC filter(LPF mostly).


Popular posts from this blog

Shell Scripting to Display Bar Graphs in Linux Terminal

 This week was quite hectic for me with course assignments and their merciless deadlines. One such assignment in Advanced Computer Architecture  was simulation of various benchmarks in alpha architecture in simplescalar , a well-known computer architecture simulator. I was supposed to run a total of 4 benchmarks with different configurations of cache memory, instruction issue widths, commit widths, in-order execution modes, etc and I had to plot the required performance parameters for every benchmark. A conservative estimate would be around 40 plots!  Since the simulation platform was Linux, I could breathe a sigh of relief since most things can be automated using a powerful tool called shell. Scripting made my life easier here since I can automate a bunch of simulations without having to keep an eye on each and every simulation which would take anywhere from 20 minutes to 20 hours.  The problem arose when it came to plotting the performance results. Because, each simulation

Programming STM32 ARM microcontrollers in Arch Linux

Once upon a time, not so long ago, the 8-bit microcontrollers were ruling the hobbyist embedded world. But today, the 32-bit ARM Cortex Microcontrollers are so inexpensive and power efficient that there is no good reason to ignore them. Here, let us see how to program a STM32 ARM cortex Microcontroller in Linux environment. The specific microcontroller used here is an STM32F103C8 (ARM cortex M3) programmed in Arch linux. Components Generic STM32F103 board (blue pill) STLINK-V2 (STM32 programmer) Female-Female connectors All the above components can be bought from ebay for less than $10 total. The STLINK-V2 is optional since you can use any of USB-SERIAL converters like FT232, CP2102, PL2303, CH340 and the built-in UART bootloader of STM32 chip to program. So if you already have any of the above serial converters, you don't really need STLINK to program the STM32F103 microcontroller. But STLINK helps if you plan to use in circuit debugging functionalities. Software The

JTAG - Test Access Port (TAP)Controller based Xilinx FPGA configuration using Raspberry Pi

JTAG - Joint Test Action Group is an IEEE 1149.1 standard used in many silicon devices for programming and debugging purposes. Xilinx FPGAs support this JTAG protocol for their configuration. Here I have designed a JTAG FPGA bitstream programmer using Raspberry Pi which programs the bit file into FPGA in fraction of seconds!  JTAG physical bus has four lines: TMS (Test Mode Select) TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) Components Used:  Raspberry-Pi Xilinx Spartan 3E FPGA (XC3S250E in Papilio One) Jumper wires BLOCK DIAGRAM: TAP CONTROLLER: The TAP(Test Access Port) controller is a state machine inside the FPGA which changes it's state based on TMS input. For instance, let us assume that the state machine is in " Test-Logic-Reset " state. Now if I drive the TMS pin low and toggle the TCK pin, the state machine will go to " Run-Test/ Idle " state. This is how we move to different states.  Note